A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In typical hardware applications, such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a fast bus transfer rate. In many computer system architectures of today, the majority of the above mentioned subsystems reside on the computer system's expansion bus.
The expansion bus is generally used as a method of adding functional components to the computer system. Devices are physically coupled to the expansion bus and use the expansion bus to communicate and exchange information. The peripheral component interconnect (PCI) bus comprises an industry standardized expansion bus architecture upon which many "peripheral" devices are manufactured. As such, the PCI bus has become a widely known and widely supported expansion bus architecture.
Prior art FIG. 1 shows a typical prior art PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge/arbiter 106 through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124. PCI bus 112 is also coupled to host PCI bridge/arbiter 106.
Referring still to prior art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, e.g., interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines. To expedite the flow of data and information, PCI bus architecture 100 supports "bus mastering". Bus mastering is the generally accepted term referring to one of the PCI agents 114-124 acquiring ownership of PCI bus 112 in order to stream line the data transfer process (e.g., to accomplish burst transfers). When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from host PCI bridge/arbiter 106. Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, host PCI bridge/arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates a transaction (e.g., data transfer) with a "target device" or destination device (e.g., main memory 104). The PCI agent granted PCI bus ownership is referred to as the "initiator device" or simply, the initiator. The protocols used in the process of acquiring, using, releasing, and configuring PCI bus 112 and PCI agents 114-124 are governed through well known and widely supported industry standards (e.g., the PCI Local Bus Specification, Revision 2.10, referred to hereafter as the PCI specification).
Bus transactions on PCI bus 112, in accordance with the PCI bus specification, are synchronous transactions. Synchronous refers to the fact that information flows from one of PCI agents 114-124 to another synchronous to the PCI bus clock. In accordance with the PCI specification, logical information (e.g., addresses, data, commands, byte enables, and the like) is evaluated with respect to the PCI bus clock. Accordingly, each initiator device and each target device operates synchronously with respect to the PCI bus clock. Arbitration for bus ownership, data transfer signals, addresses, and the like, are considered valid on the rising edge of the PCI bus clock.
There is a problem, however, in that only host PCI bridge/arbiter 106 has access to all requests from PCI agents 114-124. Each of agents 114-124 supports a dedicated request-grant signal pair coupled directly to host PCI bridge/arbiter 106. The request-grant signal pairs are used by host PCI bridge/arbiter 106 to arbitrate bus ownership as described above. No one of agents 114-124 has access to the request-grant signal pair of any other of agents 114-124. Because of this, no one of agents 114-124 can determine in advance if PCI bus 112 may be accessed without conflict.
There is another problem in that no one agent has access to any other agent's request-grant signal pairs. Where one agent may be commencing a data transfer, that agent could possibly be the target of a simultaneous data transfer, resulting in a "collision". Consequently, each of agents 114-124 is required to have built in collision detection and recovery logic, increasing their respective costs. Additionally, these collisions and possible "deadlocks" reduce the data transfer bandwidth of the of PCI bus 112.
Yet another problem is that since all logical information on PCI bus 112 is synchronous to the PCI bus clock, accesses by an agent operating in a differing clock domain can potentially render PCI bus architecture 100 unstable. An agent operating in a different clock domain functions in an essentially asynchronous manner. Its internal operations are orchestrated with respect to its own internal clock as opposed to the PCI bus clock. Where the internal clock and the PCI bus clock operate at different frequencies, the timing requirements for bus arbitration may be violated. Potentially, such violations could render PCI bus architecture 100 totally unusable.
Thus, what is required is a system which interfaces an agent operating in one clock domain to a PCI bus operating in another clock domain. What is required is a system which avoids collisions between agents. The required solution should avoid causing deadlocks, thereby and enhancing the data transfer bandwidth of the PCI bus. What is further required is a system which can determine in advance whether the PCI bus may be accessed without causing a conflict.